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E2U0053-28-81
Semiconductor MSM7728
Semiconductor Single Rail Linear CODEC
This version: Aug. 1998 MSM7728 Previous version: Apr. 1997
GENERAL DESCRIPTION
The MSM7728 is a single-channel linear CODEC CMOS IC for voice signals that contains filters for A/D and D/A conversions. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems. The analog outputs include the speaker drive output, earphone drive output and ringer output. Therefore, the sound interface can be configured with a few external circuits.
FEATURES
* Single power supply : 2.5 V to 3.6 V * Low power consumption Operating mode : 36 mW Typ. Power down mode : 0.003 mW Typ. * Digital signal input/output interface : 14-bit serial code in 2's complement format * Transmission clock frequency : 112 kHz min., 2048 kHz max. * Filter characteristics : Complies with ITU-T Recommendation G.714 * Built-in PLL eliminates a master clock * Built-in PB tone signal generator * Built-in service tone generator * Built-in ringer tone generator * General latch output: 1 bit * Both transmit and receive gain adjustable by external control * Receive interface: Speaker direct drive output Earphone interface output : 600 W, 1 mW max. Ringer output : 70 nF, 4 VPP * Transmit gain adjustable using an external resistor * Transmit microphone amplifier is eliminated by the gain setting of a maximum of 36 dB. * Built-in reference voltage supply * Serial 8-bit processor interface * Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: MSM7728GS-K)
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Semiconductor
MSM7728
BLOCK DIAGRAM
MAO MAIN - + SW1 VOL1
CODEC RC LPF 8th BPF 14 BIT ADCONV AUTO ZERO BCLK VOL2 5th LPF 14 BIT DACONV RCONT PCMOUT TCONT SYNC
SGC
SG GEN VR GEN SPK
PCMIN
RTIM
SPKP
- +
PLL SW 2 SW 4 SW CONTROL LA
SPKN
- +
VOL CONTROL EAR EAR TOUT LED RINGP RINGN VOL4 RINGER Tone - + SW 3 SW 5 Tone GEN VOL3 PB Tone SERVICE Tone POWER-DOWN CONTROL MCU INF.
WRN RDN CDOUT CDIN DCLK RSTN
SW 6
VDD AG DG
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Semiconductor
MSM7728
PIN CONFIGURATION (TOP VIEW)
SPKP SPKN EAR RINGP RINGN TOUT LED LA NC
1 2 3 4 5 6 7 8 9
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AG NC NC SGC MAO MAIN NC VDD NC NC RSTN SYNC BCLK PCMOUT PCMIN
RDN 10 CDOUT 11 WRN 12 DCLK 13 CDIN 14 DG 15
NC: No connection 30-Pin Plastic SSOP
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Semiconductor
MSM7728
PIN AND FUNCTIONAL DESCRIPTIONS
VDD Power supply pin for 2.5 to 3.6 V (Typically 3.0 V). AG Analog signal ground. DG Ground pin for the digital signal circuits. This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin on the printed circuit board. SGC Bypass capacitor pin for generating the signal ground voltage level. Insert a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. MAIN, MAO Transmit microphone input and level adjustment. MAIN is connected to the inverting input of the op-amp, and MAO is connected to the output of the op-amp. This amplifier can set up a gain to a maximum of 36dB by using an external resistor. Level adjustment should be performed in a way below. A transmit level of +6, 0, -6, or -12dB can be selected using control data from the processor interface. When CODEC is turned off, the MAO output goes high impedance.
C1 Microphone input R1
R2
MAO MAIN
- +
R1 : variable R2 > 20 kW C1 > 1/(2 3.14 30 R1) (F) Gain = R2/R1 < 63
SG
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Semiconductor SPKP, SPKN
MSM7728
These pins are used for speaker driving. The SPKN output is reversed in phase against the SPKP output when the gain is 1. The receive output signal amplitude is 2.2VPP at maximum. These outputs swing around the SG potential (signal ground potential, VDD/2) and can drive the minimum 0.6kW load in pushpull driving mode. The maximum output amplitude is 4.4VPP in pushpull driving mode (a load is inserted between SPKN and SPKP). Control data from the processor interface allows selecting the D/A conversion output, PB tone output, or service tone output and also can provide a level control and mute control. When SPK is turned off, the SG potential is output with high resistance. EAR Analog output for external accessary circuit. This output swings around the SG potential and can drive the minimum 0.6kW against the SG potential. Control data from the processor interface allows selecting the D/A conversion output, PB tone output, or service tone output and also can provide a level control and mute control. When EAR is turned off, the SG potential is output with high resistance. BCLK Shift clock signal input for PCMIN and PCMOUT. The frequency is equal to the data signaling rate. SYNC Synchronizing signal input. In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. When this signal frequency is 8 kHz, the transmit and receive paths have the frequency characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet. For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated according to the following equation: Frequency values described in the data sheet the SYNC frequency values to be actually used 8 kHz
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Semiconductor PCMIN
MSM7728
PCM signal input. A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and BCLK signal. The data signaling rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal. The PCM signal is latched into an internal register when shifted by 14 bits. The top of the data (MSD) is identified at the rising edge of SYNC. The input signal should be input in the 14-bit 2's complement format. The MSD bit represents the polarity of the signal with respect to the signal ground. PCMOUT PCM signal output. The PCM output signal is output starting with MSD in sequential order, synchronously with the rising edge of the BCLK signal. MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC. This pin is in a high impedance state except during 14-bit PCM output. It is also high impedance when the CODEC is turned off. A pull-up resistor must be connected to this pin, because its output is configured as an open drain. The output coding format is in 14-bit 2's complement. The MSD represents a polarity of the signal with respect to the signal ground. Table 1
Input/Output Level MSD +Full scale +1 0 -1 -Full scale 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 11 01 00 11 00 PCMIN/PCMOUT
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Semiconductor WRN, RDN, DCLK, CDIN, CDOUT
MSM7728
Serial control ports for microcontroller interface. Writing data to 8-bit control registers allows controling the transmit speech path/receive speech path mute, transmit speech path/receive speech path level, PB tone, service tone, and ringer. WRN is the write control signal input, RDN is the read control signal input, DCLK is the clock signal input for data shift, CDIN is the control data input, CDOUT is the control data output. When reset (RSTN=0), the control registers are reset to the initial values as described in "Control Data Description". The initial values remains unchanged until control data is written after reset. Writing of control data: When WRN is at digital "0", data that is entered in CDIN is shifted at the rising edge of the DCLK signal pulse and is latched in an internal control register. Reading of control data: When RDN is at digital "0", control data is output from CDOUT at the rising edge of a DCLK signal pulse. See Figure 2 for write and read timings. RINGP, RINGN Ringer (sounder) drive outputs. The sounder can be structured by putting a piezo-electric type sounding body (equivalent capacitance: less than 70nF) between RINGP and RINGN. LED Ringer digital level output. This pin is used for LED blinking synchronous with the ringer. LA General latch output. This output is used as a control signal for a peripheral circuit because this output can be set to digital "0" or "1" by writing data from a microcontroller interface. TOUT PB tone/service tone output. When SW6 is in the ON state, tone is output. The output resistance of this pin is approximately 10kW, which should be taken into account when using it externally. RSTN Control register reset signal input. When this pin is set to digital "0" level. All control registers are reset to the initial values. Be sure to reset the control registers after turning on the power.
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Semiconductor
MSM7728
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition
AG = DG = 0 V AG = DG = 0 V AG = DG = 0 V --
Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150
Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage Symbol VDD Ta VAIN VIH VIL Gain = 1 SYNC, BCLK, PCMIN, WRN, RDN, DCLK, CDIN, RSTN Condition -- -- Min. 2.5 -30 -- 0.45 VDD 0 Typ. 3.0 +25 -- -- -- Max. 3.6 +85 1.4 VDD 0.16 VDD 128 Fs 12 60 50 50 -- -- -- -- -- -- -- 100 -- -- -- -- -- -- -- Unit V C VPP V V
Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Sync Signal Timing High Level Sync Pulse Width *1 Low Level Sync Pulse Width *1 PCMIN Setup Time PCMIN Hold Time Digital Output Load DCLK Pulse Width
FC FS DC tIr tIf tXS tSX tWSH tWSL tDS tDH RDL CDL tWCL tWCH tWR1 tWR2 tWR3 tWR4 PWRN
BCLK SYNC BCLK SYNC, BCLK, PCMIN, WRN, RDN, DCLK, CDIN, RSTN BCLKAESYNC, See Fig.1 SYNCAEBCLK, See Fig.1 SYNC, See Fig.1 SYNC, See Fig.1 Refer to Fig.1 Refer to Fig.1 Pull-up resistor -- DCLK Low width, See Fig.2 DCLK High width, See Fig.2 DCLKAEWRNL, See Fig.2 WRNLAEDCLK, See Fig.2 DCLKAEWRNH, See Fig.2 WRNHAEDCLK, See Fig.2 --
14 Fs 4.0 40 -- -- 100 100 1 BCLK 1 BCLK 100 100 0.5 -- 50 50 50 50 50 50 9DCLK
-- 8.0 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
kHz kHz % ns ns ns ns -- -- ns ns kW pF ns ns ns --
WRN Timing
WRN Period
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz.
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Semiconductor
MSM7728
RECOMMENDED OPERATING CONDITIONS (Continued)
Parameter Symbol tRD1 RDN Timing tRD2 tRD3 tRD4 RDN Period CDIN Setup Time CDIN Hold Time Analog Input Allowable DC Offset Allowable Jitter Width PRDN tCDS tCDH Voff -- tSD PCM Data Output Delay Time tXD1 tXD2 tXD3 Control Data Output Delay Time tCD1 tCD2 -- CL = 50 pF + 1 LSTTL Pull-up resistor = 500 W See Fig.2 See Fig.2 Transmit gain stage, Gain = 0 dB Transmit gain stage, Gain = 20 dB SYNC, BCLK Condition DCLKAERDNL, See Fig.2 RDNLAEDCLK, See Fig.2 DCLKAERDNH, See Fig.2 RDNHAEDCLK, See Fig.2 -- Min. 50 50 50 50 9DCLK 50 50 -100 -10 -- 20 20 20 20 50 50 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- +100 +10 1000 100 100 100 100 -- -- ns ns Unit ns ns -- ns mV mV ns
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Semiconductor
MSM7728
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Parameter Power Supply Current Symbol IDD1 IDD2 High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output High Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIL VOL VOH IO CIN Condition
Operating mode, No signal
Min. -- -- -- 0.45 VDD 0.0 -- -- 0.0 VDD - 0.2 -- --
Typ. 20 12 70 -- -- -- -- 0.2
Max. -- -- 200 VDD 0.16 VDD 2.0 0.5 0.4
Unit mA mA mA V V mA mA V V
VDD = 3.6 V VDD = 3.0 V
Power-off mode SYNC, BCLK, PCMIN, WRN, RDN, CDIN, DCLK, RSTN -- --
PCMOUT pull-up resistor = 500 W
LA, LED, CDOUT IOL = 0.4mA LA, LED, CDOUT IOH = 1mA -- --
-- 5
10 --
mA pF
Transmit Analog Interface Characteristics
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX
MAO with respect to SG potential
Condition MAIN MAO with respect to SG potential
Min. 10 30 -- -0.7
Typ. -- -- -- -- --
Max. -- -- 30 +0.7 +20
Unit MW kW pF V mV
(DC Gain = 1)
-20
Receive Analog Interface Characteristics
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Parameter Symbol ROER EAR ROTO TOUT Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage RLSP RLER CLAO SPKP-SPKN
EAR with respect to SG potential
Condition
Min. -- -- -- 600 600 -- -1.1 -100
Typ. -- -- 10 -- -- -- -- --
Max. 10 100 -- -- -- 50 +1.1 +100
Unit W W kW W W pF V mV
ROSP SPKP, SPKN Output Resistance
Output open SPKP, SPKN, EAR, TOUT with respect to SG potential
VOAO SPKP, SPKN, EAR VOSA
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Semiconductor AC Characteristics
Parameter Symbol Loss 1 Loss 2 Overall Frequency Response Loss 3 Loss 4 Loss 5 Loss 6 Loss T1 Loss T2 Transmit Frequency Response (Expected Value) Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Receive Frequency Response (Expected Value) Loss R2 Loss R3 Loss R4 Loss R5 SD 1 SD 2 Overall Signal to Distortion Ratio SD 3 SD 4 SD 5 SD 6 SD T1 SD T2 Transmit Signal to Distortion Ratio SD T3 (Expected Value) SD T4 SD T5 SD T6 SD R1 SD R2 Receive Signal to Distortion Ratio (Expected Value) SD R3 SD R4 SD R5 SD R6 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 -10 -30 -40 -45 3 0 -10 -30 -40 -45 3 0 -10 -30 -40 -45 *1 *1 Analog to Analog *1 VDD = 2.7 to 3.3 V 0 0 0 Analog to Analog -0.2 -0.2 0 20 -0.15 -0.15 -0.15 0 -0.15 -0.15 -0.15 0.0 57.0 57.0 50.0 32.0 23.0 20.0 58 58 58 38 28 23 60 60 60 40 30 25
MSM7728
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Level Condition (dBm0) Min. 20 -0.2 Typ. -- -- Reference value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference value +0.2 +0.2 0.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dB dB dB dB Reference value +0.2 +0.2 0.8 +0.2 +0.4 +0.4 1.6 -- +0.2 dB Max. -- +0.4 dB Unit
*1
Psophometric filter is used.
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Semiconductor AC Characteristics (Continued)
Parameter Symbol GT 1 GT 2 Overall Gain Tracking GT 3 GT 4 GT 5 GT T1 Transmit Gain Tracking (Expected Value) GT T2 GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking (Expected Value) GT R2 GT R3 GT R4 GT R5 Transmit Idle Channel Noise (Expected Value) Receive Idle Channel Noise (Expected Value) Output Level (Initial value) *2 Nidle T Nidle R AV T AVSPK AVEAR AV Tt AV Rt 1020 0 -- -- 1020 1020 1020 Freq. (Hz)
MSM7728
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Level (dBm0) 3 -10 -40 -50 -55 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -- -- AIN: no signal *1 MAO-PCMOUT PCMIN-SPKP*3 PCMIN-EAR *3 VDD = 2.5 to 3.6 V Ta = -30 to +85C A to A 1020 500 0 *4 2800 2800 1020 0 0 *4
TRANS AE RECV RECV AE TRANS
Condition
Min. -0.4
Typ. +0.01 0.0 -0.03 +0.15 +0.01 0.0 -0.03 +0.15 -0.06 -0.02 -0.02 -0.27 -72 -76 0.350 0.275 -- --
Max. +0.4 +0.4 +1.0 +1.5 +0.3 +0.3 +0.6 +1.2 +0.3 +0.3 +0.6 +1.2 -68
Unit
Analog to Analog
Reference value -0.4 -1.0 -1.5 -0.3 -0.3 -0.6 -1.2 -0.3 -0.3 -0.6 -1.2 -- -- 0.312 0.245 -0.2 -0.2 dB
Reference value dB
Reference value dB
dBmOp -74 0.393 0.309 +0.2 +0.2 Vrms
Output Level (Deviation of Temperature and Power)
dB dB
Absolute Delay
Td tGD T1
0
BCLK = 128 kHz
-- -- -- -- -- -- 75 70
-- -- -- -- 0.00 0.12 85 80
0.6 0.325 0.175 0.325 0.125 0.325 -- --
ms
Transmit Group Delay
tGD T2 600 to 2600 tGD T3 tGD R1 500 to 2600 tGD R2 CR T CR R
ms
Receive Group Delay Crosstalk Attenuation
ms dB
*1 Psophometric filter is used. *2 AVT is the input level to output 0dBm0 pattern. VOL1 0dB setting. AVSPK is the level to be output from SPKP pin when 0dBm0 pattern is input. AVEAR is the level to be output from EAR pin when 0dBm0 pattern is input. *3 VOL2 0dB setting *4 The minimum value of group delay distortion is referenced. 12/23
Semiconductor AC Characteristics (Continued)
Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Symbol
MSM7728
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Min. Typ. Max. Unit 30 -- -- -- -27 -28 -16 -17 -18 -8 -1.5 -1.5 1020 0
Referenced to 0dB setting 6dBsetting -6dBsetting 6dBsetting 3dBsetting -3dBsetting -6dBsetting
Freq. Level Condition (Hz) (dBm0) 4.6 kHz to DIS 0 0 to 4000 Hz 72 kHz S 300 to 3400 fa = 470 fb = 320 0 to 50 kHz 0 -4 4.6 kHz to 100 kHz 2fa - fb
32 -37.5 -52 30 -22 -23 -11 -12 -15 -3 -- -- 6 -6 -12 6 3 -3 -6 -9 -12 -15 12 8 4 -4 -8 -12 -16
--
dB
-35 dBm0 -40 dBm0 -- -19 -20 -8 -9 -13 -1 +1.5 +1.5 7 -5 -11 7 4 -2 -5 -8 -11 -14 13.5 9.5 5.5 -2.5 -6.5 -10.5 -14.5 dB dB dB dBV dBV dB
IMD PSR T PSR R
50 mVPP Measured inband High group High group Low group VOL3 standard TOUT --
SPKP, EAR PB Acknowledge Tone Output Level V PB
VOL3 standard Low group TOUT
Service Tone Output Level PB Acknowledge Tone Frequency Distortion Service Tone Frequency Distortion VOL1 Gain Setting Value
V RT DfPB DfRT Gv11 Gv12 Gv13 Gv21 Gv22 Gv23 Gv24 Gv25 Gv26 Gv27 Gv31 Gv32 Gv33 Gv34 Gv35 Gv36 Gv37
SPKP, EAR
%
5 -7 5 2 -4 -7
-12dBsetting -13
VOL2 Gain Setting Value
1020
0
Referenced to 0dB setting
-9dBsetting -10 -12dBsetting -13 -15dBsetting -16 12dBsetting 10.5 8dBsetting
6.5 2.5
VOL3 Gain Setting Value
1020
0
Referenced to 0dB setting
4dBsetting
-4dBsetting -5.5 -8dBsetting -9.5 -12dBsetting -13.5 -16dBsetting -17.5
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Semiconductor Ringing Tone
MSM7728
(Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = -30C to +85C) Parameter Symbol
Sound volume1
Condition
Min. Typ. Max. Unit -- -- -- -- -- -- -- -- VPP
Sound volume max. 3.5 Sound volume mid.
Ringing Tone Output Amplitude
Sound volume2 730W between Sound volume4
1.5 0.5
Sound volume3 RINGP and RINGN Sound volume sma.1
Sound volume sma.2 0.25
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Semiconductor
TIMING DIAGRAMS
CODEC Interface Timing
Transmit Timing BCLK tXS SYNC
tXD1 PCMOUT
Receive Timing BCLK tRS SYNC
PCMIN
Processor Interface Timing
DCLK CDIN tWR1 WRN
, ,
1 2 3 4 5 tSX tWSH tSD MSD D2 D3 D4 1 2 3 4 5 tSR
tWSH
MSM7728
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tWSL
tXD2 D5
tXD3 D6 D7 D8 D9 D10 D11 D12 D13 D14
When tXS 1/2 * Fc, the Delay of the MSD bit is defined by tXD1. When tSX < 1/2 * Fc, the Delay of the MSD bit is defined by tSD.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tWSL
MSD
D2
D3
D4
D5
tDS D6
tDH D7 D8 D9 D10 D11 D12 D13 D14
Figure 1 Basic Timing Diagram
tWCL 3 A0 4 tCDS B4 5 B3
tWCH 6 tCDH B2 B1 7 B0 tWR3 8
1 A2 A1 tWR2
2
tWR4
PWRN RDN CDOUT H Hi-Z WRITE Mode DCLK CDIN tRD1 WRN RDN tCD1 CDOUT Hi-Z B4 B3 B2 B1 B0 tCD2 H 1 A2 A1 tRD2 2 A0 3 X 4 X PRDN 5 X 6 X tRD3 7 X tRD4 8
READ Mode
Figure 2 Processor Timing Diagram 15/23
Semiconductor
MSM7728
FUNCTIONAL DESCRIPTION
Control Data Description The MSM7728 has eight registers to control the analog pass switch, volume, and tone via an external CPU. The data interface consists of 3-bit address data and 5-bit control data in the serial 8-bit format. The register map is as shown below.
AD2 AD1 AD0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -- B4 B3 VOL3 -- -- PB tone Service tone Ringer tone Power ON/OFF B2 B1 VOL2 VOL4 LA B0 Function VOL1, VOL2 gain setting VOL3, VOL4 gain setting Read Enable Enable Enable Enable Disable Disable Disable Enable
VOL1
SW5 SW4 SW3 SW2 SW1 SW ON/OFF control SW6 Latch output/SW ON/OFF control PB tone setting ON/OFF control Service tone setting ON/OFF control Ringer tone setting ON/OFF control Power ON/OFF control
Description of Each Register CR0 - - - VOL1, VOL2 control
A2 0 A1 0 A0 0 B4 0 0 1 1 B3 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VOL2 gain setting VOL1 gain setting B2 B1 B0 Function 6dB -6dB -12dB
0dB (standard)
Remarks Simultaneous setting Standard after reset is released
0dB (standard) VOL1 and VOL2:
6dB 3dB -3dB -6dB -9dB -12dB -15dB
16/23
Semiconductor CR1 - - - VOL3, VOL4 control
A2 0 A1 0 A0 1 B4 0 0 0 0 1 1 1 1 B3 0 0 1 1 0 0 1 1 B2 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 Ringer sound volume VOL3 gain setting B1 B0 Function 12dB 8dB 4dB -4dB -8dB -12dB -16dB
Middle (standard)
MSM7728
Remarks Simultaneous setting Standard after reset is released
0dB (standard) VOL3 and VOL4:
Maximum Small 1 Small 2
CR2 - - - SWcontrol
A2 0 A1 1 A0 0 B4 B3 B2 B1 B0 Function 1: SW1 ON, 0: SW1 OFF 1: SW2 ON, 0: SW2 OFF 1: SW3 ON, 0: SW3 OFF 1: SW4 ON, 0: SW4 OFF 1: SW5 ON, 0: SW5 OFF Remarks SW1 to SW5: Simultaneous setting Standard after reset is released
CR3 - - - SW & latch control
A2 0 A1 1 A0 1 B4 0 B3 0 B2 0 B1 B0 0: LA=0, Function 0: SW6 OFF, 1: SW6 ON 1: LA=1 Remarks SW6 and LA: Simultaneous setting SW6: OFF, LA=0 after reset is released
17/23
Semiconductor CR4 - - - PB tone control
A2 1 A1 0 A0 0 B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX Code Function
MSM7728
Remarks Output destination of PB tone: EAR SPKP SPKN PB OFF after reset is released
9 0h PBtone 697Hz, 1209Hz 9 1h PBtone 697Hz, 1336Hz 9 2h PBtone 697Hz, 1477Hz 9 3h PBtone 697Hz, 1633Hz 9 4h PBtone 770Hz, 1209Hz 9 5h PBtone 770Hz, 1336Hz 9 6h PBtone 770Hz, 1477Hz 9 7h PBtone 770Hz, 1633Hz 9 8h PBtone 852Hz, 1209Hz 9 9h PBtone 852Hz, 1336Hz 9 Ah PBtone 852Hz, 1477Hz 9 Bh PBtone 852Hz, 1633Hz 9 Ch PBtone 941Hz, 1209Hz 9 Dh PBtone 941Hz, 1336Hz 9 Eh PBtone 941Hz, 1477Hz 9 Fh PBtone 941Hz, 1633Hz 8 0h PBtone OFF
CR5 - - - Service tone control
A2 A1 A0 B4 B3 B2 B1 B0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 HEX Code Frequency 400Hz 400Hz 400Hz 400Hz 1000Hz 2000Hz 400Hz/16Hz 400Hz/16Hz 400Hz/16Hz Above tones stop Intermittent Time (Note1)
Make Time Break Time1 Break Time2
Remarks Output destination of PB tone: EAR SPKP SPKN
0 B 0h 1 B 1h 0 B 2h 0 B 4h 1 B 5h 0 B 6h 1 B 9h 0 B Ah 1 B Bh 0 A 0h
0.125sec 0.125sec 0.5sec 0.25sec
Continuous Continuous Continuous
-- -- -- -- -- -- -- -- --
0.5sec 0.25sec -- -- -- 2sec
1sec 0.5sec
*
0.032sec 0.032sec
18/23
Semiconductor CR6 - - - Ringer tone control
A2 A1 A0 B4 B3 B2 B1 B0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 HEX Code Frequency Intermittent Time (Note1)
Make Time Break Time1 Break Time2
MSM7728
Remarks Output destination of PB tone: RINGP RINGN
0 D 0h 1 D 1h 0 D 2h 1 D 3h 0 D 4h 1 D 5h 0 D 6h 1 D 7h 1 D 9h 0 D Ah 1 D Bh 0 C 0h 400Hz 1kHz 2kHz Above tones stop
16Hz alternation of 2kHz/2.6kHz 16Hz alternation of 1kHz/1.3kHz
1sec 0.5sec 0.25sec
Continuous
2sec 0.5sec 0.25sec -- 2sec 0.5sec 0.25sec -- -- -- --
-- -- 2.25sec -- -- -- 2.25sec -- -- -- --
1sec 0.5sec 0.25sec
Continuous Continuous Continuous Continuous
Make time (Note1)
Break time1 Make time
Break time2
Make time
CR7 - - - Power-on/off control
A2 A1 A0 B4 B3 B2 B1 B0 1 1 1 0: SPK power-off 0: EAR power-off Function 0: CODEC power-off , 1: CODEC power-on , 1: SPK power-on , 1: EAR power-on Remarks All paths enter a power-down state after reset is released
0: toneGEN power-off , 1: toneGEN power-on
0: SG/VR/PLL power-off , 1: SG/VR/PLL power-on
19/23
Semiconductor
MSM7728
APPLICATION CIRCUIT
+V +3 V MSM7728 MAIN Microphone M MAO PCMOUT PCMIN BCLK * Speaker Auxiliary output Sounder S * * SPKP SPKN EAR RINGP RINGN LED LED General latch output LA 0.1 mF SGC AG 0V +3 V 0 to 20 W 10 mF VDD DG DCLK WRN RDN CDIN CDOUT PDN Reset input "1" = Operation "0" = Reset SYNC PCM output PCM input PCM shift clock input 8 kHz SYNC signal input
Controller
* The analog output swings at a maximum of 1.0 V above and below the VDD/2 offset level.
20/23
Semiconductor
MSM7728
APPLICATION INFORMATION
Digital pattern for 0 dBm0 The digital pattern for 0 dBm0 is shown below. (SYNC frequency = 8 kHz, signal frequency = 1 kHz)
S2
S3
S1
S4
SG
S5
S8
S6 Sample No. MSD D2 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 D3 1 0 0 1 0 1 1 0 D4 D5 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 D6 0 0 0 0 1 1 1 1 D7 1 1 1 1 0 0 0 0
S7
D8 D9 D10 D11 D12 D13 D14 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0
21/23
Semiconductor
MSM7728
NOTES ON USE
* To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and the DG pin as close as possible. Connect them to the system ground with low impedance. * Mount the device directly on the PC board. Do not use an IC socket. If use of an IC socket is unavoidable, use a short lead type socket. * When mounting the device on a frame, use electro-magnetic shielding, if any electromagnetic wave source such as power supply transformers is surrounding the device. * Keep the voltage on the VDD pin not lower than -0.3 V to avoid latch-up that may otherwise occur when power is turned on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of the device.
22/23
Semiconductor
MSM7728
PACKAGE DIMENSIONS
(Unit : mm)
SSOP30-P-56-0.65-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.19 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
23/23

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